1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming asymmetric spacers on a variety of different structures that may be formed on an integrated circuit product.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NMOS devices or PMOS devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
In the manufacture of semiconductor devices, there is a constant drive to increase the operating speed of certain integrated circuit devices such, as microprocessors, memory devices and the like. As a result of the demand for increased speed, there has been a continual reduction in the size of semiconductor devices, such as transistors. For example, in a device such as a field effect transistor (FET), device parameters, such as channel length, junction depth and gate dielectric thicknesses, to name a few, all continue to be scaled downward. In general, the smaller the channel length of the FET, the faster the transistor will operate. Moreover, by reducing the size and/or scale of the components of a typical transistor, there is also an increase in the density and number of the transistors that may be produced on a given amount of wafer real estate, thus lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Unfortunately, reducing the channel length of a transistor also increases “short channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. One example of a short channel effect includes, among other aspects, an increased drain to source leakage current when the transistor is supposed to be in the “off” or non-conductive state, due to an enlarged depletion region relative to the shorter channel length. In addition, one of the edge effects that may also adversely influence transistor performance is what is known as Miller capacitance. The Miller capacitance is a parasitic overlap capacitance that arises as a result of the doped polycrystalline silicon gate electrode and gate dielectric that (almost invariably) overlaps with a conductive portion of the more heavily doped source/drain regions and/or the less heavily doped source/drain extension (SDE) regions (if present) of the FET.
Asymmetric spacers are used for various functions during semiconductor device manufacturing. For example, if differential offsets are needed for disparate doping requirements of source or drain areas near a gate structure, oftentimes asymmetric spacers are utilized to accomplish this offset. A commonly employed technique for the formation of asymmetric spacers utilizes multiple gate structure sidewall insulator layers and multiple implantations with numerous photoresist masking and etching processes to produce the desired offset. This technique is time-consuming, and the multiple masking and etching steps add to the manufacturing costs accordingly.
The present disclosure is directed to various methods of forming asymmetric spacers on a variety of different structures that may be formed on an integrated circuit product that may avoid, or at least reduce, the effects of one or more of the problems identified above.